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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTW14N50E/D Designer'sTM Data Sheet TMOS E-FET.TM Power Field Effect Transistor TO-247 with Isolated Mounting Hole N-Channel Enhancement-Mode Silicon Gate This advanced TMOS E-FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Designed to Replace External Zener Transient Suppressor -- Absorbs High Energy in the Avalanche Mode * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature G S MTW14N50E Motorola Preferred Device TMOS POWER FET 14 AMPERES 500 VOLTS RDS(on) = 0.40 OHM (R) D CASE 340K-01, Style 1 TO-247AE MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Drain-Source Voltage Drain-Gate Voltage (RGS = 1.0 M) Gate-Source Voltage -- Continuous Drain Current -- Continuous Drain Current -- Continuous @ 100C Drain Current -- Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy -- STARTING TJ = 25C (VDD = 50 Vdc, VGS = 10 Vpk, IL = 14 Apk, L = 8.8 mH, RG = 25 ) Thermal Resistance -- Junction to Case Thermal Resistance -- Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS RJC RJA TL Value 500 500 20 14 9.0 60 180 1.44 - 55 to 150 860 0.7 40 260 Unit Vdc Vdc Vdc Adc Apk Watts W/C C mJ C/W C Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design. E-FET and Designer's are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Preferred devices are Motorola recommended choices for future use and best overall value. REV 4 (c)Motorola TMOS Power MOSFET Transistor Device Data Motorola, Inc. 1996 1 MTW14N50E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 V, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 500 Vdc, VGS = 0) (VDS = 500 Vdc, VGS = 0, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS* Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 7.0 Adc) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 14 Adc) (ID = 7.0 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 7.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS* | Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge Vd , Ad , ( (VDS = 400 Vdc, ID = 14 Adc, VGS = 10 Vdc) Vdc, Adc, (VDD = 250 Vd ID = 14 Ad VGS = 10 Vdc Vdc, RG = 4.7 ) ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS* Forward On-Voltage g Reverse Recovery Time ( (IS = 14 Adc, VGS = 0, Ad , 0, dIS/dt = 100 A/s, VGS = 0) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) *Pulse Test: Pulse Width 300 s, Duty Cycle 2%. | Switching characteristics are independent of operating junction temperature. LD LS -- -- 5.0 13 -- -- nH nH (IS = 14 Adc, VGS = 0) ( , ) (IS = 14 Adc, VGS = 0, TJ = 125C) VSD trr ta tb QRR -- -- -- -- -- -- 1.0 09 0.9 390 245 145 5.35 1.6 -- -- -- -- -- C Vdc ns -- -- -- -- -- -- -- -- 28 80 80 60 65 17 47 34 60 160 160 120 85 -- -- -- nC ns (VDS = 25 Vdc, VGS = 0, Vdc 0 f = 1.0 MHz) Ciss Coss Crss -- -- -- 2510 280 67 3510 392 94 pF VGS(th) 2.0 -- RDS(on) VDS(on) -- -- gFS 5.0 -- -- -- 6.7 5.6 -- mhos -- 3.2 7.0 0.32 4.0 -- 0.40 Vdc mV/C Ohm Vdc V(BR)DSS 500 -- IDSS -- -- IGSS -- -- -- -- 250 1000 100 nAdc -- 520 -- -- Vdc mV/C Adc Symbol Min Typ Max Unit 2 Motorola TMOS Power MOSFET Transistor Device Data MTW14N50E TYPICAL ELECTRICAL CHARACTERISTICS 20 18 I D , DRAIN CURRENT (AMPS) 16 14 12 10 8 6 4 2 0 4V 0 1 2 3 4 5 6 7 8 9 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS = 5 V TJ = 25C 10 V 7V 6V I D , DRAIN CURRENT (AMPS) 20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 9 10 TJ = 100C - 55C 25C VDS 10 V Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 1.0 VGS = 10V 0.8 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.38 0.36 0.34 0.32 0.30 0.28 0.26 0.24 0.22 0.20 0 4 8 12 16 20 ID, DRAIN CURRENT (AMPS) 24 28 VGS = 10 V VGS = 15 V TJ = 25C 0.6 TJ = 100C 0.4 TJ = 25C 0.2 TJ = -55C 0.0 0 4 8 12 16 20 ID, DRAIN CURRENT (AMPS) 24 28 Figure 3.On-Resistance versus Drain Current Figure 4.On-Resistance versus Drain Current RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2.5 100000 I DSS , DRAIN-TO-SOURCE LEAKAGE (nA) VGS = 0 V 20000 10000 2000 1000 200 100 20 10 TJ = 125C 2.0 1.5 TJ = 100C 1.0 VGS = 10 V ID = 7 A 0 50 100 150 TJ, JUNCTION TEMPERATURE (C) 200 TJ = 25C 0.5 0 - 50 0 100 200 300 400 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 500 Figure 5.On-Resistance Variation With Temperature Figure 6.Drain-To-Source Leakage Current versus Voltage Motorola TMOS Power MOSFET Transistor Device Data 3 MTW14N50E POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 10) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. 8000 7000 C, CAPACITANCE (pF) 6000 5000 4000 3000 2000 1000 0 10 5 VGS 0 VDS Crss 5 10 15 Coss VDS = 0 V VGS = 0 V TJ = 25C 10000 TJ = 25C Ciss 2000 C, CAPACITANCE (pF) 1000 VGS = 0 V Ciss 200 100 Coss Crss 20 20 25 10 1 2 20 10 100 200 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7a. Low Voltage Capacitance Variation Figure 7b. High Voltage Capacitance Variation 4 Motorola TMOS Power MOSFET Transistor Device Data MTW14N50E VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 15 VDS QT TJ = 25C ID = 14 A VDS = 400 V 500 10000 TJ = 25C ID = 14 A VDD = 250 V VGS = 10 V td(off) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) 12 400 2000 1000 9 Q1 6 Q2 VGS Q3 0 10 20 30 40 50 60 70 80 90 QT, TOTAL CHARGE (nC) 300 td(on) 200 100 tr tf 1 2 10 20 100 200 1000 200 3 100 0 100 20 10 0 RG, GATE RESISTANCE (OHMS) Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 14 I S , SOURCE CURRENT (AMPS) 12 10 8 6 4 2 0 0 0.2 0.4 0.6 0.8 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 1 TJ = 25C VGS = 0 V dIS/dt = 100 A/s Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain- to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. Motorola TMOS Power MOSFET Transistor Device Data 5 MTW14N50E I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10 s 100 s 1 ms 2 1 THERMAL LIMIT PACKAGE LIMIT RDS(on) LIMIT 1 2 20 10 100 200 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 ms E , SINGLE PULSE DRAIN-TO-SOURCE AS AVALANCHE ENERGY (mJ) 100 900 800 700 600 500 400 300 200 100 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) 150 PEAK ID = 14 A VDD = 50 V 20 10 dc 0.2 0.1 1000 Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 = 0.2 0.2 0.1 = 0.1 = 0.05 = 0.02 = 0.01 SINGLE PULSE RJC(t) = r(t) RJC RJC = 0.7C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 0.1 0.2 1 2 t, TIME (ms) 10 20 0.02 0.01 DUTY CYCLE, D = t1/t2 P(pk) t1 t2 0.002 0.001 0.01 0.02 100 200 1000 Figure 13. Thermal Response 6 Motorola TMOS Power MOSFET Transistor Device Data MTW14N50E PACKAGE DIMENSIONS -Q- TBM -T- E -B- U A 1 2 3 STYLE 1: PIN 1. 2. 3. 4. 0.25 (0.010) M C 4 L R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. MILLIMETERS MIN MAX 19.7 20.3 15.3 15.9 4.7 5.3 1.0 1.4 1.27 REF 2.0 2.4 5.5 BSC 2.2 2.6 0.4 0.8 14.2 14.8 5.5 NOM 3.7 4.3 3.55 3.65 5.0 NOM 5.5 BSC 3.0 3.4 INCHES MIN MAX 0.776 0.799 0.602 0.626 0.185 0.209 0.039 0.055 0.050 REF 0.079 0.094 0.216 BSC 0.087 0.102 0.016 0.031 0.559 0.583 0.217 NOM 0.146 0.169 0.140 0.144 0.197 NOM 0.217 BSC 0.118 0.134 K P -Y- GATE DRAIN SOURCE DRAIN V F D 0.25 (0.010) M H J G DIM A B C D E F G H J K L P Q R U V YQ S CASE 340K-01 ISSUE O Motorola TMOS Power MOSFET Transistor Device Data 7 MTW14N50E Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 8 Motorola TMOS Power MOSFET TransistorMTW14N50E/D Device Data *MTW14N50E/D* |
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